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| Preliminary 74LCXZ16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) February 2000 Revised February 2000 74LCXZ16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) General Description The LCXZ16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. When VCC is between 0 and 1.5V, the LCXZ16240 is in the high impedance state during power up or power down. This places the outputs in the high impedance (Z) state preventing intermittent low impedance loading or glitching in bus oriented applications. The LCXZ16240 is designed for low voltage (2.7V or 3.3V) VCC applications with capacity of interfacing to a 5V signal environment. The LCXZ16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s Guaranteed power up/down high impedance s Supports live insertion/withdrawal s 2.7V-3.6V VCC specifications provided s 4.5 ns tPD max (VCC = 3.3V), 20 A ICC max s 24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74LCXZ16240MEA 74LCXZ16240MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Logic Symbol Pin Descriptions Pin Names OEn I0-I15 O0-O15 Description Output Enable Inputs (Active LOW) Inputs Outputs (c) 2000 Fairchild Semiconductor Corporation DS500257 www.fairchildsemi.com Preliminary 74LCXZ16240 Truth Tables Inputs OE1 L L H I0-I3 L H X Outputs O0-O3 H L Z OE3 L L H Inputs I8-I11 L H X Outputs O8-O11 H L Z Inputs OE2 L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Outputs I4-I7 L H X O4-O7 H L Z OE4 L L H Inputs I12-I15 L H X Outputs O12-O15 H L Z Functional Description The LCXZ16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram www.fairchildsemi.com 2 Preliminary 74LCXZ16240 Absolute Maximum Ratings(Note 1) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150 (Note 3) Min Operating HIGH or LOW State 3-STATE or VCC = OFF IOH/IOL TA t/V Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V -40 0 2.7 0 0 0 Max 3.6 5.5 VCC 5.5 24 12 85 10 Units V V V mA C ns/V Output in 3-STATE or VCC = 0-1.5V Output in HIGH or LOW State (Note 2) VI < GND VO < GND VO > VCC Conditions Units V V V mA mA mA mA mA C Recommended Operating Conditions Symbol VCC VI VO Supply Voltage Input Voltage Output Voltage Parameter Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF IPU/PD ICC ICC Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Power Up/Down 3-STATE Output Current Quiescent Supply Current Increase in ICC per Input 0 VI 5.5V 0 VO 5.5V VI = V IH or VIL VI or VO = 5.5V VO = 0.5V to VCC VI = GND or VCC VI = V CC or GND 3.6V VI, VO 5.5V (Note 4) VIH = VCC -0.6V Note 4: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 3.0 3.0 2.7 - 3.6 2.7 3.0 3.0 2.7 - 3.6 2.7 - 3.6 0 0 - 1.5 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 TA = -40C to +85C Min 2.0 0.8 VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5.0 5.0 10 5.0 225 225 500 Max Units V V V V A A A A A A 3 www.fairchildsemi.com Preliminary 74LCXZ16240 AC Electrical Characteristics TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 5) Output Disable Time Propagation Delay Data to Output Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 Max 4.5 4.5 5.4 5.4 5.3 5.3 1.0 1.0 VCC = 2.7V CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 5.3 5.3 6.0 6.0 5.4 5.4 ns ns ns ns Units Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V VCC (V) 3.3 3.3 TA = 25C Typical 0.8 -0.8 V V Unit Capacitance Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF www.fairchildsemi.com 4 Preliminary 74LCXZ16240 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) VI 6V for VCC = 3.3V, 2.7V VCC * 2 for VCC = 2.5V CL 50 pF 30 pF Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V trise and tfall 5 www.fairchildsemi.com Preliminary 74LCXZ16240 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 Preliminary 74LCXZ16240 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com Preliminary 74LCXZ16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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